[Rechenwerk] Setze HW-Aufwand D-FF als Tikz Zeichnung um
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@ -573,8 +573,8 @@ Jein, denn $1$ Taktzyklus dauert deutlich mehr als doppelt solang wie die Berech
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\begin{tabular}{@{}l@{}l}
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\begin{tabular}{@{}l@{}l}
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1 \acs{VA} & $ =18$ Transistoren \\
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1 \acs{VA} & $ =18$ Transistoren \\
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2 \acs{D-FF} = $2\cdot 6$ & $ =12$ Transistoren. \hspace*{12.5mm} \textit{(siehe \autoref{fig:serielladdierer_2} rechts)} \\
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2 \acs{D-FF} = $2\cdot 6$ & $ =12$ Transistoren. \hspace*{12.5mm} \textit{(siehe \autoref{fig:schieberegister})} \\
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3 $n$-Bit-\acs{SR} & $ =3\cdot 6n = 18n$ Transistoren \textit{(siehe \autoref{fig:serielladdierer_2} links)} \\
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3 $n$-Bit-\acs{SR} & $ =3\cdot 6n = 18n$ Transistoren \textit{(siehe \autoref{fig:aufwand_dff})} \\
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Takterzeugung~~ & \textit{(im folgenden nicht näher betrachtet)} \\
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Takterzeugung~~ & \textit{(im folgenden nicht näher betrachtet)} \\
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\textbf{gesamt} & $18n+30$ Transistoren
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\textbf{gesamt} & $18n+30$ Transistoren
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\end{tabular}
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\end{tabular}
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@ -584,9 +584,48 @@ Zum Vergleich: \acs{RC-PA}: $18n-10$, \dash der \acl{SA} braucht 40 Transistoren
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\begin{figure}[h!]
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\begin{figure}[h!]
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\centering
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\centering
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\includegraphics[width=15cm]{Bilder/Serielladdierer_2.png}
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\begin{subfigure}[h]{0.47\textwidth}
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\caption{Schieberegister und D-Flip-Flop}
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\medskip
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\label{fig:serielladdierer_2}
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\includegraphics[width=\textwidth]{Bilder/Serielladdierer_2.png}
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\medskip
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\caption{4-Bit Schieberegister}
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\label{fig:schieberegister}
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\end{subfigure}
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~
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\begin{subfigure}[h]{0.47\textwidth}
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\begin{tikzpicture}[scale=0.9,font=\sffamily, circuit logic IEC, large circuit symbols,
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knoten/.style={circle,fill,draw,inner sep=0pt,minimum size=1.5mm}]
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\node[nand gate, inputs={inn}] at (0,1) (NAND1) {};
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\node[nand gate, inputs={nnn}] at (0,-1) (NAND2) {};
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\node at (-2,0) (T) {T};
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\node[right=of NAND1] (Q1) {Q*};
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\node[right=of NAND2] (Q2) {Q~};
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\node[knoten] at ($(Q1)+(-0.6,0)$) (K2) {};
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\node[knoten] at ($(Q2)+(-0.6,0)$) (K3) {};
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\draw (K2) -- ($(K2)+(0,-0.7)$)
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-- ($(NAND2.input 2) + (-0.4,0.5)$)
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|- (NAND2.input 1);
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\draw (K3) -- ($(K3)+(0,0.7)$)
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-- ($(NAND1.input 3) + (-0.4,-0.5)$)
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|- (NAND1.input 3);
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\node[] at ($(NAND2.input 3) + (-2.8,0)$) (D) {D};
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\draw (T) -- ($(T)+(1,0)$) |- (NAND1.input 2);
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\draw ($(T)+(1,0)$) |- (NAND2.input 2);
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\node[knoten] at ($(T)+(1,0)$) {};
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\draw (Q1) -- (NAND1.output) (Q2) -- (NAND2.output);
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\draw (NAND1.input 1) -- ($(NAND1.input 1) + (-2,0)$) |- ($(NAND2.input 3) + (-2,0)$) -- (NAND2.input 3);
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\draw ($(NAND2.input 3) + (-2,0)$) -- ($(NAND2.input 3) + (-2.4,0)$);
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\node[knoten] at ($(NAND2.input 3) + (-2.12,0)$) {};
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\end{tikzpicture}
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\caption{Hardwareaufwand für einen D-FF: 6 Tr.}
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\label{fig:aufwand_dff}
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\end{subfigure}
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\caption{Schieberegister aus D-FF mit Hardwareaufwand}
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\end{figure}
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\end{figure}
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\begin{Achtung}
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\begin{Achtung}
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