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[Rechenwerk] Setze HW-Aufwand D-FF als Tikz Zeichnung um

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Andre Meyering 2017-12-08 18:02:30 +01:00
parent fd6f1fb6fc
commit 92d5ceddf8
Signed by: Andre
GPG key ID: AA6B4FC2A2C4329A
2 changed files with 46 additions and 7 deletions
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53
Kapitel/03_Rechenwerk.tex
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@ -572,10 +572,10 @@ Jein, denn $1$ Taktzyklus dauert deutlich mehr als doppelt solang wie die Berech
\subsection{Hardwareaufwand ($N$-Bit-SA)}
\begin{tabular}{@{}l@{}l}
1 \acs{VA} & $ =18$ Transistoren \\
2 \acs{D-FF} = $2\cdot 6$ & $ =12$ Transistoren. \hspace*{12.5mm} \textit{(siehe \autoref{fig:serielladdierer_2} rechts)} \\
3 $n$-Bit-\acs{SR} & $ =3\cdot 6n = 18n$ Transistoren \textit{(siehe \autoref{fig:serielladdierer_2} links)} \\
Takterzeugung~~ & \textit{(im folgenden nicht näher betrachtet)} \\
1 \acs{VA} & $ =18$ Transistoren \\
2 \acs{D-FF} = $2\cdot 6$ & $ =12$ Transistoren. \hspace*{12.5mm} \textit{(siehe \autoref{fig:schieberegister})} \\
3 $n$-Bit-\acs{SR} & $ =3\cdot 6n = 18n$ Transistoren \textit{(siehe \autoref{fig:aufwand_dff})} \\
Takterzeugung~~ & \textit{(im folgenden nicht näher betrachtet)} \\
\textbf{gesamt} & $18n+30$ Transistoren
\end{tabular}
@ -584,9 +584,48 @@ Zum Vergleich: \acs{RC-PA}: $18n-10$, \dash der \acl{SA} braucht 40 Transistoren
\begin{figure}[h!]
\centering
\includegraphics[width=15cm]{Bilder/Serielladdierer_2.png}
\caption{Schieberegister und D-Flip-Flop}
\label{fig:serielladdierer_2}
\begin{subfigure}[h]{0.47\textwidth}
\medskip
\includegraphics[width=\textwidth]{Bilder/Serielladdierer_2.png}
\medskip
\caption{4-Bit Schieberegister}
\label{fig:schieberegister}
\end{subfigure}
~
\begin{subfigure}[h]{0.47\textwidth}
\begin{tikzpicture}[scale=0.9,font=\sffamily, circuit logic IEC, large circuit symbols,
knoten/.style={circle,fill,draw,inner sep=0pt,minimum size=1.5mm}]
\node[nand gate, inputs={inn}] at (0,1) (NAND1) {};
\node[nand gate, inputs={nnn}] at (0,-1) (NAND2) {};
\node at (-2,0) (T) {T};
\node[right=of NAND1] (Q1) {Q*};
\node[right=of NAND2] (Q2) {Q~};
\node[knoten] at ($(Q1)+(-0.6,0)$) (K2) {};
\node[knoten] at ($(Q2)+(-0.6,0)$) (K3) {};
\draw (K2) -- ($(K2)+(0,-0.7)$)
-- ($(NAND2.input 2) + (-0.4,0.5)$)
|- (NAND2.input 1);
\draw (K3) -- ($(K3)+(0,0.7)$)
-- ($(NAND1.input 3) + (-0.4,-0.5)$)
|- (NAND1.input 3);
\node[] at ($(NAND2.input 3) + (-2.8,0)$) (D) {D};
\draw (T) -- ($(T)+(1,0)$) |- (NAND1.input 2);
\draw ($(T)+(1,0)$) |- (NAND2.input 2);
\node[knoten] at ($(T)+(1,0)$) {};
\draw (Q1) -- (NAND1.output) (Q2) -- (NAND2.output);
\draw (NAND1.input 1) -- ($(NAND1.input 1) + (-2,0)$) |- ($(NAND2.input 3) + (-2,0)$) -- (NAND2.input 3);
\draw ($(NAND2.input 3) + (-2,0)$) -- ($(NAND2.input 3) + (-2.4,0)$);
\node[knoten] at ($(NAND2.input 3) + (-2.12,0)$) {};
\end{tikzpicture}
\caption{Hardwareaufwand für einen D-FF: 6 Tr.}
\label{fig:aufwand_dff}
\end{subfigure}
\caption{Schieberegister aus D-FF mit Hardwareaufwand}
\end{figure}
\begin{Achtung}