DHBW_AI_16/Rechnerarchitektur_Roethig
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[Serielladdierer] Fixe Grafik

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This commit is contained in:
Andre Meyering 2017-12-08 18:00:53 +01:00
parent 1c15e587dd
commit fd6f1fb6fc
Signed by: Andre
GPG key ID: AA6B4FC2A2C4329A
1 changed files with 6 additions and 2 deletions
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Kapitel/03_Rechenwerk.tex
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@ -531,7 +531,9 @@ $\Rightarrow$ damit ist das $n$ der nicht-\acs{CLA-PA} noch klein $\Rightarrow$
\draw (3,2.7) -- ++(0.75,0) |- (cout);
\draw (-1,2.8) -- ++(2,0);
\node at (0,2.5) {$s_n$};
\node at (0,2.2) {$s_n$};
\draw (0,2.8) -- ++(0,-0.4);
\node[knoten] at (0,2.8) {};
% Gate: NOT
\node[not gate] at (0.5,5) (NOT) {};
@ -639,7 +641,9 @@ Zum Vergleich: \acs{RC-PA}: $18n-10$, \dash der \acl{SA} braucht 40 Transistoren
\draw (3,2.7) -- ++(0.75,0) |- (cout);
\draw (-1,2.8) -- ++(2,0);
\node at (0,2.5) {$s_n$};
\node at (0,2.2) {$s_n$};
\draw (0,2.8) -- ++(0,-0.4);
\node[knoten] at (0,2.8) {};
% Gate: NOT
\node[not gate] at (0.5,5) (NOT) {};